Zuspec Backend HDLSim

The Zuspec HDLSim backend enables co-simulation of Zuspec testbench descriptions with existing HDL designs (SystemVerilog/Verilog). It bridges Python-based Zuspec test environments with hardware simulators, allowing you to drive HDL designs from Python tests while executing critical paths in hardware simulation.

The backend integrates with DV Flow Manager (DFM) to provide automated, declarative workflows for generating, building, and running HDL testbenches.

Contents:

• Overview
  • What is Zuspec Backend HDLSim?
  • Key Capabilities
  • When to Use HDLSim Backend
  • Architecture Approach
  • Comparison with Other Zuspec Backends
  • Next Steps
• Architecture
  • System Architecture
  • Component Classification
  • Domain Separation Rules
  • Generation Flow
  • Code Generation Details
  • Key Classes
• Quick Start
  • Prerequisites
  • Installation
  • Step 1: Define Your Components
  • Step 2: Create Your Test
  • Step 3: Create Workflow Specification
  • Step 4: Create RTL
  • Step 5: Generate and Run
  • What Happens at Runtime
  • Next Steps
  • Troubleshooting
• Components
  • Component Types
  • Component Bindings
  • Profile and Checker
  • Best Practices
  • Common Patterns
• DV Flow Manager Integration
  • Overview
  • GenTB Task
  • Flow Specification Example
  • Simulator Integration
  • Running Tasks
  • Advanced Patterns
  • Working with Filesets
  • Debugging
  • Best Practices
  • See Also
• API Reference
  • Core Modules
  • Type Definitions
  • Examples
  • See Also
• Examples
  • Example 1: Simple Counter
  • Example 2: Wishbone Bus
  • Example 3: Multi-Component System
  • See Also