Zuspec Backend HDLSim
=====================

The Zuspec HDLSim backend enables co-simulation of Zuspec testbench descriptions with 
existing HDL designs (SystemVerilog/Verilog). It bridges Python-based Zuspec test 
environments with hardware simulators, allowing you to drive HDL designs from Python 
tests while executing critical paths in hardware simulation.

The backend integrates with `DV Flow Manager (DFM) <https://dv-flow.github.io>`_ to 
provide automated, declarative workflows for generating, building, and running HDL testbenches.

.. toctree::
   :maxdepth: 2
   :caption: Contents:

   overview
   architecture
   quickstart
   components
   dfm_integration
   api_reference
   examples